1. Technical Field
The present invention generally relates to a semiconductor apparatus, and more particularly, to a voltage generation circuit, and a write driver and a semiconductor memory apparatus including the same.
2. Related Art
A volatile memory apparatus such as a DRAM has a disadvantage in that, because a memory cell is constituted by a capacitor, stored data cannot be retained when the power supply is interrupted. In order to overcome such a disadvantage, a nonvolatile memory apparatus has been developed, in which a memory cell is constituted by a resistance variable device such as a phase change device to retain data even when the power supply is interrupted.
FIG. 1 is a diagram showing a resistive memory cell MC and a write voltage for writing data in the memory cell. The resistive memory cell MC is constituted by a resistance variable device, and has a resistance value that changes according to a voltage VWRT or current IWRT flowing through it. In particular, in the case where the resistance variable device is a phase change device, the memory cell MC can be converted into a crystalline state and an amorphous state according to the current IWRT to store specific data. In general, a set voltage SET is needed to convert the memory cell MC into the crystalline state, and a reset voltage RESET is needed to convert the memory cell MC into the amorphous state.
The set voltage SET and the reset voltage RESET should be generated as shown in the graph of FIG. 1. The reset voltage RESET may be generated by applying a voltage of a high level to the memory cell MC for a short time, and the set voltage SET may be generated by applying a voltage of a level lower than the reset voltage RESET for a long time. Specifically, the set voltage SET should have a slow quenching slope that decreases slowly to convert the memory cell MC into the crystalline state. The x-axis showing time TIME.
FIG. 2 is a diagram showing the configuration of a conventional voltage generation circuit 10 for generating a ramp voltage VRAMP used to generate the set voltage SET of FIG. 1 and the ramp voltage VRAMP generated by the voltage generation circuit. In FIG. 2, the voltage generation circuit 10 includes a DAC (digital-to-analog converter) 11, a power application unit 12, a plurality of switches, and current sources which are coupled in series with the plurality of switches.
The DAC 11 generates code signals C<0:5> which turn on or off the plurality of switches to generate the ramp voltage VRAMP. The levels of the respective bits of the code signals C<0:5> may vary with the lapse of time TIME. When an enable signal EN is applied, the power application unit 12 applies a power supply voltage VDD to a node from which the ramp voltage VRAMP is generated, such that the ramp voltage VRAMP reaches a predetermined level. Thereafter, when the switches are turned on by the code signals C<0:5>, the node from which the ramp voltage VRAMP is generated is discharged to a ground voltage VSS through the current sources. Thus, the ramp voltage VRAMP may decrease in a step-like pattern as shown in the graph of FIG. 2 and may generate a slow quenching pulse.
However, in the voltage generation circuit 10, since the level of the ramp voltage VRAMP is controlled according to the code signals C<0:5> generated by the DAC 11, a problem is caused in that the ramp voltage VRAMP is not likely to be normally generated according to level variations of the respective bits of the code signals C<0:5>. For example, in the case where the MSB (most significant bit) of the code signals C<0:5> generated by the DAC 11 varies, a serious glitch may occur as shown in FIG. 3A (i.e., Glitch Occurrence), so the ramp voltage VRAMP is not normally generated. Also, due to the linear characteristic of the DAC 11, a slope at which the ramp voltage VRAMP decreases may be irregularly changed as shown in FIG. 3B (i.e., Slope change or Normal Slope). Abnormal generation of the ramp voltage VRAMP may influence the set voltage SET which writes data to the memory cell, and thus, the memory cell may not be converted into a desired crystalline state. As a consequence, a phenomenon is likely to occur, in which incorrect data is written to the memory cell.